1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and, more particularly, relates to a semiconductor integrated circuit including a Buit-In Self Test (BIST) circuit.
2. Description of the Related Art
For a semiconductor integrated circuit with a built-in writable/readable memory, a method is known in which a fault is detected by testing the memory using a BIST circuit (memory BIST circuit). As shown in FIG. 14, a BIST circuit (memory BIST circuit) 30 generates memory write test data TD1, an address signal TA and a memory control signal TWEN, and sends this information to a memory 50. Memory read test data TQ1 is read out of the memory 50 in accordance with the memory write test data TD1, address signal TA and memory control signal TWEN. If the BIST circuit 30 is “comparator-based”, the BIST circuit 30 compares the memory read test data TQ1 with an expected value generated in the BIST circuit 30 and determines whether or not the memory 50 is defective. Alternatively, if the BIST circuit 30 is “compactor-based”, the BIST circuit 30 sequentially compacts the memory read test data TQ1, compares a final compacted result with an expected value which has been calculated beforehand, and determines whether or not the memory 50 is defective. Since the BIST circuit 30 is operated with only external clocks, it is possible to test the memory 50, without performing complicated controls.
Accordingly, it is easy to test the memory 50 by using the BIST circuit 30 in parallel with another test such as a test on a logic circuit 3.
For a test on the logic circuit 3, a scan test and a test using a logic BIST circuit are known. In the scan test, by using a scan design technique, a plurality of registers (flip-flops) in the logic circuit 3 are replaced by scan registers, and the scan registers are connected in series with each other, directly externally controlled, and observed. A test pattern can be made by regarding logic parts other than the registers in the logic circuit 3 as a combinational circuit, an output of which is uniquely determined by an input condition. On the other hand, the memory 50 connected with the logic circuit 3 sequentially operates and therefore cannot be regarded as a combinational circuit. Accordingly, the memory 50 is difficult to handle when making a test pattern.
Therefore, in general, as schematically shown in FIG. 14, a bypass circuit 40x is placed between the logic circuit 3 and the memory 50. The bypass circuit 40x propagates logic circuit test data D1 to D3 to bypass the memory 50, from an input of the memory 50 to an output thereof. In FIG. 14, an exclusive OR (logic circuit test data) D0 of the logic circuit test data D1 to D3 is transferred to the logic circuit 3 by using an exclusive-OR gate 52a. It is necessary to include switching circuits (multiplexers) 41x to 41z in the bypass circuit 40x which, when the memory 50 is tested, switch inputs to the memory 50 from the logic circuit test data D1 to D3 to the memory write test data TD1, address signal TA and memory control signal TWEN from the BIST circuit 30. Further, it is necessary to include a multiplexer 43x in the bypass circuit 40x, which switches inputs to the logic circuit 3 from system data to the logic circuit test data DO when the logic circuit 3 is tested and vice versa when normal operation is performed.
As shown in FIG. 14, in testing of the logic circuit 3, the logic circuit test data D1 to D3 from the logic circuit 3 are branched at the inputs of the multiplexers 41x to 41z, respectively, and, after passing through the exclusive-OR gate 52a and the multiplexer 43x, propagated to the logic circuit 3. On the other hand, in testing of the memory 50, the multiplexers 41x to 41z select the memory write test data TD1, address signal TA and memory control signal TWEN from the BIST circuit 30, respectively, and transfer this information to the memory 50. The memory read test data TQ1 is branched at the input of the multiplexer 43x and transferred to the BIST circuit 30. That is, the logic circuit test data D0 to D3 for the test on the logic circuit 3 pass along different signal lines from those for the memory write test data TD1, address signal TA, memory control signal TWEN, and memory read test data TQ1 for the test on the memory 50. Accordingly, it is possible to test the logic circuit 3 and the memory 50 in parallel and therefore to reduce time for the tests.
However, in the bypass circuit 40x, neither the logic circuit test data D0 to D4 for the test on the logic circuit 3 nor the memory write test data TD1, address signal TA, memory control signal TWEN, and memory read test data TQ1 for the test on the memory 50 pass along signal lines L11 to L13 and L17 between the multiplexers 41x to 41z and 43x, and the branching points on the inputs thereof, respectively. Accordingly, the signal lines L11 to L13 and L17 are left non-tested, and therefore the fault coverage is decreased.
In comparison with the bypass circuit 40x, in a bypass circuit 40y shown in FIG. 15, branching points to the exclusive-OR gate 52a and the memory 50 are provided at the outputs of the multiplexers 41x to 41z so that no signal line is left non-tested. Moreover, a branching point to the logic circuit 3 and the BIST circuit 30 is provided at the output of the multiplexer 43x. According to the bypass circuit 40y, if the logic circuit 3 and the memory 50 are sequentially tested, all the signal lines can be tested. In the bypass circuit 40, however, the logic circuit test data D1 to D3, and the memory write test data TD, address signal TA and memory control signal TWEN pass along the same signal lines L14 to 16, respectively. Further, the memory read test data TQ1 and the logic circuit test data D0 pass along the same signal line L18. That is to say, the signal lines are overlapped. Therefore, the logic circuit 3 and the memory 50 cannot be tested in parallel, and accordingly, test time cannot be reduced.